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Ordering number : EN5834
CMOS IC
LC74799, 74799M
On-Screen Display Controller IC
Overview
The LC74799 and LC74799M are on-screen display controller CMOS ICs that display characters and patterns on the TV screen under microprocessor control. These ICs include a built-in PDC/VPS/UDT interface circuit.
Package Dimensions
unit: mm 3193-DIP30SD
[LC74799]
Features
* Display format: 24 characters by 12 rows (Up to 288 characters) * Character format: 12 (horizontal) x 18 (vertical) dots * Character sizes: Three sizes each in the horizontal and vertical directions * Characters in font: 128 * Initial display positions: 64 horizontal positions and 64 vertical positions * Blinking: Specifiable in character units * Blinking types: Two periods supported: 1.0 second and 0.5 second * Blanking: Over the whole font (12 x 18 dots) * Background color -- 8 colors (internal synchronization mode): 4fSC -- 6 colors (internal synchronization mode): 2fSC -- Blue background only: NTSC * Line background color -- Three lines can be set up. -- 8 line background colors (in internal synchronization mode): 4fSC -- 6 line background colors (in internal synchronization mode): 2fSC * External control input: 8-bit serial input format * On-chip sync separator and AFC circuits * On-chip PDC/VPS/UDT interface circuit (Supports the I2C bus standard) * Video outputs: PAL and NTSC format composite video outputs * Package: DIP30SD (400 mil) MFP30S (375 mil)
SANYO: DIP30SD
unit: mm 3216-MFP30S
[LC74799M]
SANYO: MFP30S
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
51898RM (OT) No. 5834-1/32
LC74799, 74799M Pin Assignment
No. 5834-2/32
LC74799, 74799M Pin Descriptions
Pin No. 1 2 Pin name VSS1 XtalIN Crystal oscillator 3 XtalOUT (MUTE) (MUTE input) Ground Function Ground connection (digital system ground) These pins are used either to connect the crystal and capacitors used to form an external crystal oscillator circuit to generate the internal synchronizing signals, or to input an external clock signal (2fsc or 4fsc). As a mask option, the XtalOUT pin can be set to function as the MUTE input pin. When this pin is set low, the video output is held at the pedestal level. (A pull-up resistor is built in and the input has hysteresis characteristics.) Switches the mode between external clock input and crystal oscillator operation. A low level selects crystal oscillator operation and a high level selects external clock input. As a mask option, the CTRL1 input pin can be set to function as the CHABLK (character * frame) output. This is a 3-value output. This pin must be left open. Clock input Input for the PDC/VPS data output clock. I2C bus PDC/VPS data output. I2C bus write address: [01111100] I2C bus read address: [01111101] Notes
4
CTRL1 (CHABLK) NC SCL
Crystal oscillator input switching (CHABLK output)
5 6
7
SDA
Data output
8
SYNCJDG
Outputs the state of the external synchronizing signal presence/absence judgment. External synchronizing signal judgment Outputs a high level when synchronizing signals are present. output Outputs the crystal oscillator clock when CS1 and RST are low. (This signal is not output on command resets.) Enable input 1 Enable input for the OSD serial data input. Serial data input is enabled when this pin is low. A pull-up resistor is built in and the input has hysteresis characteristics. Serial data input enable pin. A pull-up resistor is built in and the input has hysteresis characteristics. Serial data input. A pull-up resistor is built in and the input has hysteresis characteristics. Composite video signal level adjustment power supply (analog system power supply) Charge pump output. Connect a low-pass filter to this pin. VCO oscillator control voltage input. (For data slicing) Ground (VCO ground) VCO oscillator range adjustment resistor connection VCO oscillator control voltage input. For character display. Power supply (+5 V: VCO power supply) Composite video signal output Ground (analog system ground) Composite video signal input SECAM chrominance signal input Power supply (+5 V: digital system power supply) Video signal input to the internal sync separator circuit Internal sync separator circuit adjustment Internal sync separator circuit composite synchronizing signal output. Can be switched to function as a signal (high, low, or ST. pulse) output by the MOD0 setting when SEL0 is high. Inputs the vertical synchronizing signal created by integrating the SEPOUT pin output signal. An integration circuit must be connected between this pin and the SEPOUT pin. This pin must be tied to VDD1 if unused. This pin is valid when CTL3 is set high. Background color phase adjustment resistor connection System reset input. A pull-up resistor is built in and the input has hysteresis characteristics. Power supply (+5 V: digital system power supply)
9
CS1
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
SCLK1 SIN1 VDD2 CPOUT VCOIN VSS3 VCOR VCOIN2 VDD3 CVOUT VSS2 CVIN CVCR VDD1 SYNIN SEPC SEPOUT
Clock input 1 Data input 1 Power supply Charge pump output Oscillator control voltage input Ground Oscillator range adjustment Oscillator control voltage input 2 Power supply (+5 V) Video signal output Ground Video signal input Video signal input Power supply (+5 V) Sync separator circuit input Sync separator circuit adjustment Composite synchronizing signal output
27
SEPIN
Vertical synchronizing signal input
28 29 30
CDLR RST VDD1
Background color phase adjustment Reset input Power supply (+5 V)
Note *: A capacitor of at least 2000 pF must be connected between the VDD1 power supply and VSS1.
No. 5834-3/32
LC74799, 74799M
Specifications
Absolute Maximum Ratings
Parameter Maximum supply voltage Maximum input voltage Maximum output voltage Allowable power dissipation Operating temperature Storage temperature Symbol VDD max VIN VOUT Pd max Topr Tstg VDD1 and VDD2 All input pins DOUT, SEPOUT, SYNCJDG Ta = 25C Conditions Ratings VSS - 0.3 to VSS + 7.0 VSS - 0.3 to VDD + 0.3 VSS - 0.3 to VDD + 0.3 350 -30 to +70 -40 to +125 Unit V V V mW C C
Allowable Operating Ranges
Parameter Symbol VDD1 VDD2 VIH1 VIH2 VIL1 VIL2 RPU VIN1 VIN2 VIN3 FOSC1 VDD1 and VDD2 VDD2 RST, CS1, CS2, SIN1, SCLK1, SCLK2, MUTE CTRL1 RST, CS1, CS2, SIN1, SCLK1, SCLK2, MUTE CTRL1 RST, CS1, CS2, SIN1, SCLK1, SCLK2, MUTE Applies to pins set up by options. CVIN and CVCR: VDD1 = 5 V SYNIN : VDD1 = 5 V XtalIN (when used for external clock input) fIN = 2fsc or 4fsc: VDD1 = 5 V XtalIN and XtalOUT oscillator pins (2fsc : PAL) XtalIN and XtalOUT oscillator pins (4fsc : PAL) 1.5 0.10 8.867 17.734 Conditions Ratings min 4.5 4.5 0.8 VDD1 0.7 VDD1 VSS - 0.3 VSS - 0.3 25 50 2.0 2.0 2.5 5.0 typ 5.0 5.0 max 5.5 1.27 VDD1 VDD1 + 0.3 VDD1 + 0.3 0.2 VDD1 0.3 VDD1 90 Unit V V V V V V k Vp-p Vp-p Vp-p MHz MHz
Supply voltage
Input high-level voltage
Input low-level voltage Pull-up resistance Composite video signal input voltage Input voltage Oscillator frequencies
Note: Applications must be especially cautious about noise when using the XtalIN input pin in clock input mode.
Electrical Characteristics at Ta = -30 to +70C, VDD1 = 5 V unless otherwise specified.
Parameter Input off leakage current Output off leakage current Output high-level voltage Symbol Ileak1 Ileak2 VOH1 VOL1 VOL2 Three-value output voltage VO CVIN and CVCR CVOUT DOUT, SEPOUT, CPOUT, and SYNCJDG VDD1 = 4.5 V, IOH = -1.0 mA DOUT, SEPOUT, CPOUT, and SYNCJDG VDD1 = 4.5 V, IOL = -1.0 mA SDA: VDD1 = 5.0 V, IOL = 3.0 mA H CHABLK: VDD1 = 5.0 V M L IIH Input current IIL IDD1 IDD2 SYNC level VSN RST, CS1, CS2, SIN, SCLK1, SCLK2, CTRL1, MUTE, SEPIN, VCOIN, and VCOIN2, VIN = VDD1 CTRL1, SEPIN, VCOIN, and VCOIN2, VIN = VSS1 VDD1: With all outputs open Xtal : 17.734 MHz, VCO : 27 MHz VDD2 : VDD2 = 5 V CVOUT : VDD1 = 5.0 V, VDD2 = 5.0 V CVOUT : VDD1 = 5.0 V, VDD2 = 5.0 V CVOUT : VDD1 = 5.0 V, VDD2 = 5.0 V (1) (2) (3) (1) (2) (3) (1) (2) (3) 0.80 1.00 1.40 1.37 1.57 1.97 1.07 1.27 1.67 -1 40 20 3.3 1.8 0 3.5 1.0 0.4 5.0 2.3 0.8 1 Conditions Ratings min typ max 1 1 Unit A A V V V V V V A A mA mA V V V V V V V V V
Output low-level voltage
Operating mode current drain
Pedestal level
VPD
Color burst low level
VCBL
Continued on next page.
No. 5834-4/32
LC74799, 74799M
Continued from preceding page.
Parameter Symbol Conditions (1) (2) (3) (1) (2) (3) (1) (2) (3) (1) (2) (3) (1) (2) (3) (1) (2) (3) Ratings min typ 1.67 1.87 2.27 1.23 (1.16) 1.43 (1.36) 1.83 (1.76) 2.37 (2.01) 2.57 (2.21) 2.97 (2.61) 1.50 1.70 2.10 2.08 2.28 2.68 2.65 2.85 3.25 max Unit V V V V V V V V V V V V V V V V V V
Color burst high level
VCBH
CVOUT : VDD1 = 5.0 V, VDD2 = 5.0 V CVOUT : VDD1 = 5.0 V, VDD2 = 5.0 V CVOUT : VDD1 = 5.0 V, VDD2 = 5.0 V CVOUT : VDD1 = 5.0 V, VDD2 = 5.0 V CVOUT : VDD1 = 5.0 V, VDD2 = 5.0 V CVOUT : VDD1 = 5.0 V, VDD2 = 5.0 V
Background color low level
VRSH
Background color high level
VRSL
Frame level 0
VBK0
Frame level 1
VBK1
Character level
VCHA
Notes: (1): When the sync level = 0.8 V (2): When the sync level = 1.0 V (3): When the sync level = 1.4 V The values in parentheses for the background high and low levels are for blue background mode.
Timing Characteristics at Ta = -30 to +70C, VDD1 = 5 0.5 V
Parameter OSD write (See figure 1.) Minimum input pulse width tW (SCLK) tW (CS1) tSU (CS1) tSU (SIN) th (CS1) th (SIN) tword twt tSCL tBUF tHD ; STA tLOW tHIGH tHD ; DAT tSU ; DAT tR tF tSU ; STO 4.0 4.7 4.0 4.7 4.0 0 250 1000 300 SCLK1 CS1 (The period when CS1 is high) CS1 SIN1 CS1 SIN1 The 8-bit data write time The RAM data write time 200 1 200 200 2 200 4.2 1 ns s ns ns s ns s s Symbol Conditions Ratings min typ max Unit
Data setup time
Data hold time
One word write time
PDC/VPS write and read (I2C bus timing) SCL frequency Bus release time Start hold time SCL low-level period SCL high-level period Data hold time Data setup time Rise time Fall time Stop setup time 100 kHz s s s s s ns ns ns s
No. 5834-5/32
LC74799, 74799M
Figure 1 OSD Serial Data Input Timing
S: Start condition P: Stop condition
Note: DOUT goes to the high-impedance state while CS2 is high.
Figure 2 PDC/VPS Serial Timing (I2C bus)
No. 5834-6/32
Serial parallel converter Horizontal character size register Vertical character size Horizontal display position Vertical display position Blinking and reverse video control Display control register RAM write address counter
System Block Diagram
8-bit latch + command decoder
Data output buffer
Output control
AFC circuit data slicing Horizontal display position Vertical display position
AFC circuit for character display
Decoder
Data slicer
Horizontal size counter Vertical size counter Horizontal dot counter Blinking and reverse video control
Vertical dot counter
Display RAM
LC74799, 74799M
Character control counter
Line control counter
Decoder
Font ROM
Sync discrimination
Data peak hold circuit (data slicing) Composite sync signal separation control Timing generator
HSYNC peak hold (HSYNC slicing)
Pedestal clamp
Sync signal generator
Character output control Background control Video output control
Shift register
No. 5834-7/32
LC74799, 74799M Display Control Commands Display control commands have an 8-bit format and are transferred using the serial input function. Commands consist of a command identification code in the first byte and command data in the following bytes. The following commands are supported. 1 COMMAND0: Display memory (VRAM) write address setup command 2 COMMAND1: Display character data write command 3 COMMAND2: Vertical display start position and vertical character size setup command 4 COMMAND3: Horizontal display start position and horizontal character size setup command 5 COMMAND4: Display control setup command 6 COMMAND5: Display control setup command 7 COMMAND6: Synchronizing signal detection setup command 8 COMMAND7 to COMMAND12: Display control setup commands 9 COMMAND13 to COMMAND17: VPS/PDC control commands. These commands can be written using the I2C bus. Display Control Command Table
First byte Command Command identification code 7 COMMAND0 (Write address setup) COMMAND1 (Character write) COMMAND2 (Vertical character size and vertical display start position) COMMAND3 (Horizontal character size and horizontal display start position) COMMAND4 (Display control) COMMAND5 (Display control) COMMAND6 (Synchronizing signal detection) COMMAND7 (Display control) COMMAND8 (Display control) COMMAND9 (Display control) COMMAND10 (Display control) COMMAND11 (Display control) COMMAND12 (Display control) COMMAND13 (VPS/PDC control) COMMAND14 (VPS/PDC control) COMMAND15 (VPS/PDC control) COMMAND16 (VPS/PDC control) COMMAND17 (VPS/PDC control) 1 1 1 1 1 0 0 1 0 1 1 1 1 1 0 0 0 0 ECP 19 0 1 1 1 1 0 1 1 1 0 1 1 1 1 0 1 1 0 0 1 1 1 1 0 1 0 1 0 1 1 1 1 0 1 0 1 0 VIN NP CPA 1 1 1 1 1 0 1 0 0 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 0 1 0 0 1 1 1 1 0 0 0 1 0 1 1 1 1 1 1 1 0 SEL 0 0 MOD 0 0 DIS LIN 0 0 0 MUT 0 1 1 0 1 1 1 0 0 1 0 1 1 1 0 1 0 VS 21 HS 21 TST MOD NP1 VS 20 HS 20 RAM ERS NP0 VS 11 HS 11 OSC STP NON VS 10 HS 10 SYS RST INT 0 0 BLK 2 RSH LV2 RN 2 CIN SEL LNA 3 LNB 3 LNC 3 0 0 0 0 FS VP 5 HP 5 BLK 1 HLF INT RN 1 CIN CTL LNA 2 LNB 2 LNC 2 VSP DCK VIN 2 CPA 0 RN 0 VNP SEL LNA 1 LNB 1 LNC 1 VSP SLC SEL 22 0 SN 3 VSP SEL LNA 0 LNB 0 LNC 0 LNC SEL HLF TON VPM 3 HBS 1 ECV 13 ECP 16 ECP 23 ECV 12 ECP 15 ECP 22 ECV 11 ECP 14 ECP 21 ECV 5 ECP 13 ECP 20 VP 4 HP 4 BLK 0 BCL VP 3 HP 3 BK 1 CB VP 2 HP 2 BK 0 PH 2 SN 2 MSK ERS LPA 2 LPB 2 LPC 2 MOD 3 SEL 2 VPM 2 BMS PH 1 SN 1 MSK SEL LPA 1 LPB 1 LPC 1 LNB SEL SEL 1 VPM 1 EMS LPA 0 LPB 0 LPC 0 MOD 2 CTL 3 VPM 0 DCE VP 1 HP 1 RV VP 0 HP 0 DSP ON PH 0 SN 0 EGL 1 0 0 1 0 0 0 0 at c6 c5 c4 c3 c2 c1 c0 1 6 0 5 0 4 0 3 V3 2 V2 Data 1 V1 0 V0 7 0 6 0 5 0 4 H4 Second byte Data 3 H3 2 H2 1 H1 0 H0
VMW VMW HBS SE2 0 SEL ECV 15 ECP 18 ECP 25 2 ECV 14 ECP 17 ECP 24
Once written, a first byte command identification code is stored until the next first byte is written. However, when the display character data write command (COMMAND1) is written, the LC74799/M locks into the display character data write mode, and another first byte cannot be written. When the CS pin is set high, the LC74799/M is set to the COMMAND0 (display memory write address setup mode) state.
No. 5834-8/32
LC74799, 74799M COMMAND0 (Display memory write address setup command) * First byte
DA 0 to 7 7 6 5 4 3 Register -- -- -- -- V3 Contents State 1 0 0 0 0 1 0 1 0 1 0 1 Display memory line address (0 to B hexadecimal) Command 0 identification code. Sets the display memory write address. Function Notes
2
V2
1
V1
0
V0
* Second byte
DA 0 to 7 7 6 5 4 Register -- -- -- H4 Contents State 0 0 0 0 1 0 1 0 1 0 1 0 1 Display memory column address (0 to 17 hexadecimal) Function Second byte identification bit Notes
3
H3
2
H2
1
H1
0
H0
Note: All registers are set to 0 when the LC74799/M is reset by the RST pin.
COMMAND1 (Display character data write setup command) * First byte
DA 0 to 7 7 6 5 4 3 2 1 0 Register -- -- -- -- -- -- -- -- Contents State 1 0 0 1 0 0 0 0 Command 1 identification code. Sets up display character data write mode. When this command is input, the LC74799/M locks in the display character data write mode until the CS pin goes high. Function Notes
No. 5834-9/32
LC74799, 74799M * Second byte
DA 0 to 7 7 Register Contents State 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Character code (00 to 7F hexadecimal) Character attribute off Character attribute on Function Notes
at
6
c6
5
c5
4
c4
3
c3
2
c2
1
c1
0
c0
Note: All registers are set to 0 when the LC74799/M is reset by the RST pin.
COMMAND2 (Vertical display start position and vertical character size setup command) * First byte
DA 0 to 7 7 6 5 4 3 Register -- -- -- -- VS21 Contents State 1 0 1 0 0 1 0 1 0 1 0 1
VS11 VS21 VS20
Function
Notes
Command 2 identification code. Sets the vertical display start position and the vertical character size.
0 1H/dot 3H/dot
1 2H/dot 1H/dot Second line vertical character size
0 1
VS10
2
VS20
1
VS11
0 1H/dot 3H/dot
1 2H/dot 1H/dot First line vertical character size
0 1
0
VS10
* Second byte
DA 0 to 7 7 6 Register -- FS VP5 (MSB) VP4 Contents State 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Character display area The vertical display start position is set by the 6 bits VP0 to VP5. The weight of bit 1 is 2H. Function Second byte identification bit Crystal oscillator frequency: 2fsc Crystal oscillator frequency: 4fsc If VS is the vertical display start position then: VS = H x 2 2n VPn
n=0
Notes
5
(
5
)
H: the horizontal synchronization pulse period
4
3
VP3
2
VP2
1
VP1 VP0 (LSB)
0
Note: All registers are set to 0 when the LC74799/M is reset by the RST pin.
No. 5834-10/32
LC74799, 74799M COMMAND3 (Horizontal display start position and horizontal size setup command) * First byte
DA 0 to 7 7 6 5 4 3 Register -- -- -- -- HS21 Contents State 1 0 1 0 0 1 0 1 0 1 0 1
HS11 HS21 HS20
Function Command 3 identification code. Sets the horizontal display start position and the horizontal character size.
Notes
0 1Tc/dot 3Tc/dot
1 2Tc/dot 1Tc/dot Second line horizontal character size
0 1
HS10
2
HS20
1
HS11
0 1Tc/dot 3Tc/dot
1 2Tc/dot 1Tc/dot First line horizontal character size
0 1
0
HS10
* Second byte
DA 0 to 7 7 6 5 Register -- -- HP5 (MSB) HP4 Contents State 0 0 0 1 0 1 0 1 0 1 0 1 0 1 If HS is the horizontal start position then: HS = Tc x 2 2n HPn
n=0
Function Second byte identification bit
Notes
4
3
HP3
(
5
)
2
HP2
The horizontal display start position is set by the 6 bits HP0 to HP5. The weight of bit 1 is 2Tc.
Tc: Period of the oscillator in operating mode.
1
HP1 HP0 (LSB)
0
Note: All registers are set to 0 when the LC74799/M is reset by the RST pin.
No. 5834-11/32
LC74799, 74799M COMMAND4 (Display control setup command) * First byte
DA 0 to 7 7 6 5 4 3 Register -- -- -- -- TSTMOD Contents State 1 1 1 0 0 1 0 1 0 1 OSCSTP 1 0 1 Reset all registers and turn display off Erase display RAM. (The RAM data is set to 7F hexadecimal.) Do not stop the crystal and VCO oscillators Stop the crystal and VCO oscillators Normal operating mode Test mode Erasing RAM takes about 500 s. (This operation must be executed in the DSPOFF state.) Valid in external synchronization mode when character display is off. It will no longer be possible to detect VPS/PDC data The registers are reset when the CS pin is low, and the reset state is cleared when CS is set high This bit must be set to 0 Command 4 identification code. Display character data write setup. Function Notes
2
RAMERS
0
SYSRST
* Second byte
DA 0 to 7 7 6 Register -- BLK2 Contents State 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1
BLK1
Function Second byte identification bit Character display area Video display area
BLK0
Notes
Specifies the size for complete fill in
5
BLK1
0 Blanking off Frame size
1 Character size Complete fill in size Switches the blinking period Blinking in reverse video mode switches the display between normal character display and reverse video display Changes the blanking size
0 1 Blinking period: About 0.5 s Blinking period: About 1.0 s Blinking off Blinking on Reverse video off Reverse video on Character display off Character display on
4
BLK0
3
BK1
2
BK0
1
RV
0
DSPON
Note: All registers are set to 0 when the LC74799/M is reset by the RST pin.
No. 5834-12/32
LC74799, 74799M COMMAND5 (Display control setup command) * First byte
DA 0 to 7 7 6 5 4 3 Register -- -- -- -- NP1 Contents State 1 1 0 1 0 1 0 1 0 1 0 1 NTSC PAL 525 lines 625 lines Interlaced Noninterlaced External synchronization Internal synchronization Switches between interlaced and noninterlaced video Switches between external and internal synchronization Modified by the external input signal V Switches between NTSC and PAL Command 5 identification code. Display control setup. Function Notes
2
NP0
1
NON
0
INT
* Second byte
DA 0 to 7 7 6 Register -- RSHLV2 Contents State 0 0 1 0 1 0 1 0 1 0 2 PH2 1 0 1 PH1 1 0 0 PH0 1 Note: All registers are set to 0 when the LC74799/M is reset by the RST pin. Function Second byte identification bit Background color level 1 (level that is different from blue) Background color level 2 (level that is identical to the blue level) Normal mode Partial internal synchronization mode Background color on No background color (Only the background level is set) Color burst signal output Color burst signal output stopped Only valid when BCL is high Only valid in internal synchronization mode Switches the background color signal level Notes
5
HLFINT
4
BCL
3
CB
PH2 0 0 0 0 1 1 1 1
PH1 0 0 1 1 0 0 1 1
PH0 0 1 0 1 0 1 0 1
Background color (phase) Cyan* Yellow* Red* Blue* Cyan blue Green* Orange Magenta* *: When 2fsc is used. Background color specification
No. 5834-13/32
LC74799, 74799M COMMAND6 (Synchronizing signal detection setup command) * First byte
DA 0 to 7 7 6 5 4 3 Register -- -- -- -- SEL0 Contents State 1 1 1 0 0 1 0 1 0 1 0 1 12 lines 10 lines Normal output CVIN is cut and CVOUT is held at the pedestal level CVOUT switching
SEL0 MOD0
Function
Notes
Command 6 identification code. Sets up synchronizing signal control.
0 DAV CSYNC
1 Sliced data width ST.PULSE Switches the number of lines displayed Switches the SEPOUT (pin 26) output
0 1
2
MOD0
1
DISLIN
0
MUT
* Second byte
DA 0 to 7 7 6 Register -- RN2 Contents State 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 SN3 0 0 0 0 1 SN2 0 0 0 1 0 SN1 0 0 1 0 0 SN0 0 1 0 0 0 Number of times HSYNC detected Not detected 32 times 64 times 128 times 256 times External synchronizing signal detection control. Signal present signal absent transition detection. Sets the sampling period in which SYNC cannot be detected continuously in the horizontal synchronizing signal period (1H). Function Second byte identification bit RN2 0 0 0 1 RN1 0 0 1 0 RN0 0 1 0 0 Number of times HSYNC detected 32 times 4 times 8 times 16 times External synchronizing signal detection control. Signal absent signal present transition detection. Sets the sampling period in which SYNC can be detected continuously in the horizontal synchronizing signal period (1H). Notes
5
RN1
4
RN0
3
SN3
2
SN2
1
SN1
0
SN0
Note: All registers are set to 0 when the LC74799/M is reset by the RST pin.
No. 5834-14/32
LC74799, 74799M COMMAND7 (Display control setup command) * First byte
DA 0 to 7 7 6 5 4 3 2 1 0 Register -- -- -- -- -- -- -- -- Contents State 1 1 1 1 0 0 0 0 Extended command 0 identification code Command 7 identification code. Display control setup. Function Notes
* Second byte
DA 0 to 7 7 6 Register -- CINSEL Contents State 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Function Second byte identification bit Blank area (the logical OR of the character and frame signals) Video signal display area CVCR: off CVCR: on V falling edge detection V rising edge detection VSEP: about 8.9 s (for NTSC) VSEP: about 17.8 s (for NTSC) Mask valid Mask invalid 3H (NTSC) 20H (NTSC) Frame level 0 only (VBK0) Two-stage frame level (VBK0 and VBK1) Switches the frame level. (Only valid when BLK0 is 0 and BLK1 is 1.) Switches the VSYNC mask Clears the HSYNC and VSYNK masks CVCR on signal switching CVCR on/off switching Switches the V acquisition polarity in external mode when internal V separation is used Switches the internal V separation period Notes
5
CINCTL
4
VNPSEL
3
VSPSEL
2
MSKERS
1
MSKSEL
0
EGL
Note: All registers are set to 0 when the LC74799/M is reset by the RST pin.
No. 5834-15/32
LC74799, 74799M COMMAND8 (Display control setup command) * First byte
DA 0 to 7 7 6 5 4 3 2 1 0 Register -- -- -- -- -- -- -- -- Contents State 1 1 1 1 0 0 0 1 Extended command 1 identification code Command 7 identification code. Display control setup. Function Notes
* Second byte
DA 0 to 7 7 Register -- Contents State 0 0 6 LNA3 1 0 5 LNA2 1 0 4 LNA1 1 0 3 LNA0 1 0 2 LPA2 1 0 1 LPA1 1 0 0 LNA0 1 Note: All registers are set to 0 when the LC74799/M is reset by the RST pin. Function Second byte identification bit LNA3 LNA2 LNA1 LNA0 0 0 0 0 0 0 0 0 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 0 0 1 1 0 0 1 1 0 0 1 1 -- 0 1 0 1 0 1 0 1 0 1 0 1 -- Specified line Do not change the line background Line 1 Line 2 Line 3 Line 4 Line 5 Line 6 Line 7 Line 8 Line 9 Line 10 Line 11 Line 12 Specifies the line whose background is to be changed. (This specification is illegal for the same line as LNA*, LNB*, and LNC*) Notes
LPA2 0 0 0 0 1 1 1 1
LPA1 0 0 1 1 0 0 1 1
LPA0 0 1 0 1 0 1 0 1
Background color (phase) Cyan* Yellow* Red* Blue* Cyan blue Green* Orange Magenta* *: When 2fsc is used. Specifies the background color
No. 5834-16/32
LC74799, 74799M COMMAND9 (Display control setup command) * First byte
DA 0 to 7 7 6 5 4 3 2 1 0 Register -- -- -- -- -- -- -- -- Contents State 1 1 1 1 0 0 1 0 Extended command 2 identification code Command 7 identification code. Display control setup. Function Notes
* Second byte
DA 0 to 7 7 Register -- Contents State 0 0 6 LNB3 1 0 5 LNB2 1 0 4 LNB1 1 0 3 LNB0 1 0 2 LPB2 1 0 1 LPB1 1 0 0 LNB0 1 Note: All registers are set to 0 when the LC74799/M is reset by the RST pin. Function Second byte identification bit LNB3 LNB2 LNB1 LNB0 0 0 0 0 0 0 0 0 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 0 0 1 1 0 0 1 1 0 0 1 1 -- 0 1 0 1 0 1 0 1 0 1 0 1 -- Specified line Do not change the line background Line 1 Line 2 Line 3 Line 4 Line 5 Line 6 Line 7 Line 8 Line 9 Line 10 Line 11 Line 12 Specifies the line whose background is to be changed. (This specification is illegal for the same line as LNA*, LNB*, and LNC*) Notes
LPB2 0 0 0 0 1 1 1 1
LPB1 0 0 1 1 0 0 1 1
LPB0 0 1 0 1 0 1 0 1
Background color (phase) Cyan* Yellow* Red* Blue* Cyan blue Green* Orange Magenta* *: When 2fsc is used. Specifies the background color
No. 5834-17/32
LC74799, 74799M COMMAND10 (Display control setup command) * First byte
DA 0 to 7 7 6 5 4 3 2 1 0 Register -- -- -- -- -- -- -- -- Contents State 1 1 1 1 0 0 1 1 Extended command 3 identification code Command 7 identification code. Display control setup. Function Notes
* Second byte
DA 0 to 7 7 Register -- Contents State 0 0 6 LNC3 1 0 5 LNC2 1 0 4 LNC1 1 0 3 LNC0 1 0 2 LPC2 1 0 1 LPC1 1 0 0 LNC0 1 Note: All registers are set to 0 when the LC74799/M is reset by the RST pin. Function Second byte identification bit LNC3 LNC2 LNC1 LNC0 0 0 0 0 0 0 0 0 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 0 0 1 1 0 0 1 1 0 0 1 1 -- 0 1 0 1 0 1 0 1 0 1 0 1 -- Specified line Do not change the line background Line 1 Line 2 Line 3 Line 4 Line 5 Line 6 Line 7 Line 8 Line 9 Line 10 Line 11 Line 12 Specifies the line whose background is to be changed. (This specification is illegal for the same line as LNA*, LNB*, and LNC*) Notes
LPC2 0 0 0 0 1 1 1 1
LPC1 0 0 1 1 0 0 1 1
LPC0 0 1 0 1 0 1 0 1
Background color (phase) Cyan* Yellow* Red* Blue* Cyan blue Green* Orange Magenta* *: When 2fsc is used. Specifies the background color
No. 5834-18/32
LC74799, 74799M COMMAND11 (Display control setup command) * First byte
DA 0 to 7 7 6 5 4 3 2 1 0 Register -- -- -- -- -- -- -- -- Contents State 1 1 1 1 0 1 0 0 Extended command 4 identification code Command 7 identification code. Display control setup. Function Notes
* Second byte
DA 0 to 7 7 6 5 Register -- -- VSPDCK Contents State 0 0 0 1 0 1 0 3 LNCSEL 1 0 2 MOD3 1 0 1 LNBSEL 1 0 0 MOD2 1 Character display VCO operating Character display VCO stopped Data slice VCO operating Data slice VCO stopped Normal line background color operation RV characters have the background color specified by PH* and the RV character background color is white The LNCSEL = 1 setting specifications RV characters have the background color specified by PH* and characters are white Normal line background color operation RV characters have the background color specified by PH* and the RV character background color is white. The LNBSEL = 1 setting specifications RV characters have the background color specified by PH* and characters are white Valid when LNBSEL is high Valid when LNCSEL is high Switches the RV mode background color for the line specified by LNB* for characters specified for RV display Data slice VCO control Character display VCO control Function Second byte identification bit Notes
4
VSPSLC
Switches the RV mode background color for the line specified by LNB* for characters specified for RV display
Note: All registers are set to 0 when the LC74799/M is reset by the RST pin.
No. 5834-19/32
LC74799, 74799M COMMAND12 (Display control setup command) * First byte
DA 0 to 7 7 6 5 4 3 2 1 0 Register -- -- -- -- -- -- -- -- Contents State 1 1 1 1 0 1 0 1 Extended command 5 identification code Command 7 identification code. Display control setup. Function Notes
* Second byte
DA 0 to 7 7 6 Register -- VINNP Contents State 0 0 1 0 1 0 4 SEL22 1 0 3 HLFTON 1 0 2 SEL2 1 1 SEL1 0 1 0 1 Vertical synchronization signal input (external synchronization) Frame signal input Internal V separation used Internal V separation not used (external V separation) SEPIN (pin 27) input switching. Only valid when CTL3 is high. V separation switching SEL22 0 0 0 0 1 1 1 SEL2 0 0 1 1 0 0 1 HLFTOM 0 1 0 1 0 1 0 Output SYNCJDG Halftone O/E LOCK SYNDET2 SENDET LOCK2 SYNCJDG pin (pin 8) output switching. The halftone output line specification depends on background color specification (the logical or of the 3-line specification) SYNCDET2: Used for character display LOCK2: Used for character display Function Second byte identification bit Negative CSYNC input polarity Positive CSYNC input polarity Normal input CSYNC input to the SEPIN pin SEPIN pin input switching CSYNC input polarity selection Notes
5
VIN2
0
CTL3
Note: All registers are set to 0 when the LC74799/M is reset by the RST pin.
No. 5834-20/32
LC74799, 74799M COMMAND13 (VPS/PDC control setup command) Only using the I2C bus * First byte
DA 0 to 7 7 6 5 4 3 2 1 0 Register -- -- -- -- -- -- -- -- Contents State 1 1 1 1 0 1 0 1 Extended command 5 identification code Command 7 identification code. Display control setup. Function Notes
* Second byte
DA 0 to 7 7 Register -- Contents State 0 0 6 CPA1 1 0 5 CPA0 1 4 -- 0 0 3 VPM3 1 0 2 VPM2 1 0 1 VPM1 1 0 0 VPM0 1 VPM3 VPM2 VPM1 VPM0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Operating mode VPS 8/30/2 (PDC) Automatic PDC/VPS switching 8/30/1 (UDT) Header time 1 Header time 2 Header time 3 Header time 4 Status display 1 Status display 2 Status display 3 Status display 4 PAL Pulse Automatic PDC/VPS switching 2 CPA1 0 0 1 1 CPA0 0 1 0 1 Clock No.4 No.3 No.2 No.1 Data acquisition clock switching Function Second byte identification bit Notes
Note: All registers are set to 0 when the LC74799/M is reset by the RST pin.
No. 5834-21/32
LC74799, 74799M COMMAND14 (VPS/PDC control setup command) Only using the I2C bus * First byte
DA 0 to 7 7 6 5 4 3 2 1 0 Register -- -- -- -- -- -- -- -- Contents State 1 1 1 1 0 1 1 0 Extended command 6 identification code Command 7 identification code. Display control setup. Function Notes
* Second byte
DA 0 to 7 7 6 Register -- VMWSE2 Contents State 0 0 1 0 1 0 1 0 1 0 2 BMS 1 0 1 EMS 1 Error check invalid (Applications can select whether data for which an error is detected is held or writing on a per-byte basis.) Data hold Data write (When the error bit is 0 in VPS mode.) Error checking enabled for unused data bytes. VPS: bytes 3, 4, and 6 to 10, PDCC (8/30/2): bytes 7 to 12, header 1: bytes 14 to 37, header 2: bytes 14 to 29, header 3: bytes 14 to 21, status 1 (3): bytes 7 to 25, status 2 (4): bytes 7 to 35 Error checking disabled for unused data bytes. VPS: bytes 3, 4, and 6 to 10, PDCC (8/30/2): bytes 7 to 12, header 1: bytes 14 to 37, header 2: bytes 14 to 29, header 3: bytes 14 to 21, status 1 (3): bytes 7 to 25, status 2 (4): bytes 7 to 35 Function Second byte identification bit V mask period start - From the retrace period V mask period start - From 10H before the retrace period The V mask period is the retrace period The V mask period is 9H Discrimination mode 1 Discrimination mode 2 Discrimination mode 1 Discrimination mode 2 Error check valid (Error checking can be turned on or off on a per-byte basis.) When set to 0, if there are no errors in bytes for which error checking is turned on, those bytes are written to P-S. When set to 1, all bytes are written to P-S regardless of the error status. Specifies handling of bytes for which error checking is set to off but in which an error occurred when error checking is turned on. Framing code Clock line CPOUT pin (pin 13) V mask period switching CPOUT pin (pin 13) V mask period switching 2 Notes
5
VMWSEL
4
HBS2
3
HBS1
0
0
DCE
Error checking setting for unused data bytes. Biphase (VPS), Hamming (PDC), and odd parity (header).
1
Note: All registers are set to 0 when the LC74799/M is reset by the RST pin.
No. 5834-22/32
LC74799, 74799M COMMAND15 (VPS/PDC control setup command) Only using the I2C bus * First byte
DA 0 to 7 7 6 5 4 3 2 1 0 Register -- -- -- -- -- -- -- -- Contents State 1 1 1 1 0 1 1 1 Extended command 7 identification code Command 7 identification code. Display control setup. Function Notes
* Second byte
DA 0 to 7 7 6 Register -- -- Contents State 0 0 0 5 ECV15 1 0 4 ECV14 1 0 3 ECV13 1 0 2 ECV12 1 0 1 ECV11 1 0 0 ECV5 1 Byte 5 biphase error check off (Data write) Byte 11 biphase error check off (Data write) Byte 5 biphase error check on (Data hold) Byte 12 biphase error check off (Data write) Byte 11 biphase error check on (Data hold) Byte 13 biphase error check off (Data write) Byte 12 biphase error check on (Data hold) Byte 14 biphase error check off (Data write) Byte 13 biphase error check on (Data hold) Byte 15 biphase error check off (Data write) Byte 14 biphase error check on (Data hold) Byte 15 biphase error check on (Data hold) Specification when the VPS data BMS bit is 0. The item in parentheses is the specification when the VPS data BMS bit is 1. Function Second byte identification bit Notes
Note: All registers are set to 0 when the LC74799/M is reset by the RST pin.
No. 5834-23/32
LC74799, 74799M COMMAND16 (VPS/PDC control setup command) Only using the I2C bus * First byte
DA 0 to 7 7 6 5 4 3 2 1 0 Register -- -- -- -- -- -- -- -- Contents State 1 1 1 1 1 0 0 0 Extended command 8 identification code Command 7 identification code. Display control setup. Function Notes
* Second byte
DA 0 to 7 7 Register -- Contents State 0 0 6 ECP19 1 Byte 19 Hamming error check off (Data write) {Bytes 44, 28, 36, 20, 32, 42, 32, and 42} Byte 18 Hamming error check on (Data hold) {Bytes 43, 27, 35, 19, 31, 41, 31, and 41} Byte 18 Hamming error check off (Data write) {Bytes 43, 27, 35, 19, 31, 41, 31, and 41} Byte 17 Hamming error check on (Data hold) {Bytes 42, 26, 34, 18, 30, 40, 30, and 40} Byte 17 Hamming error check off (Data write) {Bytes 42, 26, 34, 18, 30, 40, 30, and 40} Byte 16 Hamming error check on (Data hold) {Bytes 41, 25, 33, 17, 29, 39, 29, and 39} Byte 16 Hamming error check off (Data write) {Bytes 41, 25, 33, 17, 29, 39, 29, and 39} Byte 15 Hamming error check on (Data hold) {Bytes 40, 24, 32, 16, 28, 38, 28, and 38} Byte 15 Hamming error check off (Data write) {Bytes 40, 24, 32, 16, 28, 38, 28, and 38} Byte 14 Hamming error check on (Data hold) {Bytes 39, 23, 31, 15, 27, 37, 27, and 37} Byte 14 Hamming error check off (Data write) {Bytes 39, 23, 31, 15, 27, 37, 27, and 37} Byte 13 Hamming error check on (Data hold) {Bytes 38, 22, 30, 14, 26, 36, 26, and 36} Byte 13 Hamming error check off (Data write) {Bytes 38, 22, 30, 14, 26, 36, 26, and 36} Function Second byte identification bit Byte 19 Hamming error check on (Data hold) {Bytes 44, 28, 36, 20, 32, 42, 32, and 42} Specification when the PDC data (8/30/2) BMS bit is 0. The item in parentheses is the specification when the BMS bit is 1. The item in curl braces lists the odd parity check on/off bytes for header modes 1, 2, 3, and 4 and status mode 1, 2, 3, and 4. Notes
0 5 ECP18 1 0 4 ECP17 1 0 3 ECP16 1 0 2 ECP15 1 0 1 ECP14 1 0 0 ECP13 1
Note: All registers are set to 0 when the LC74799/M is reset by the RST pin.
No. 5834-24/32
LC74799, 74799M COMMAND17 (VPS/PDC control setup command) Only using the I2C bus * First byte
DA 0 to 7 7 6 5 4 3 2 1 0 Register -- -- -- -- -- -- -- -- Contents State 1 1 1 1 1 0 0 1 Extended command 9 identification code Command 7 identification code. Display control setup. Function Notes
* Second byte
DA 0 to 7 7 6 Register -- -- Contents State 0 0 0 5 ECP25 1 Byte 25 Hamming error check off (Data write) Byte 25 Hamming error check on (Data hold) Specification when the PDC data (8/30/2) BMS bit is 0. The item in parentheses is the specification when the BMS bit is 1. The item in curly braces lists the odd parity check off bytes for header modes 1, 2, 3, and 4 and status mode 1, 2, 3, and 4. Function Second byte identification bit Notes
4
ECP24
0 1 0 1 0
Byte 24 Hamming error check on (Data hold) Byte 24 Hamming error check off (Data write) Byte 23 Hamming error check on (Data hold) Byte 23 Hamming error check off (Data write) Byte 22 Hamming error check on (Data hold) {Bytes -, -, -, -, 35, 45, 35, and 45} Byte 22 Hamming error check off (Data write) {Bytes -, -, -, -, 35, 45, 35, and 45} Byte 21 Hamming error check on (Data hold) {Bytes -, -, -, -, 34, 44, 34, and 44} Byte 21 Hamming error check off (Data write) {Bytes -, -, -, -, 34, 44, 34, and 44} Byte 20 Hamming error check on (Data hold) {Bytes 45, 29, 37, 21, 33, 43, 33, and 43} Byte 20 Hamming error check off (Data write) {Bytes 45, 29, 37, 21, 33, 43, 33, and 43}
3
ECP23
2
ECP22 1 0
1
ECP21 1 0
0
ECP20 1
Note: All registers are set to 0 when the LC74799/M is reset by the RST pin.
No. 5834-25/32
LC74799, 74799M PDC/VPS Output Data Format Data is output in order starting with bit 7 of byte 1.
Output data Byte 1 Bit 7 6 5 4 3 2 1 0 Byte 2 Bit 7 6 5 4 3 2 1 0 Byte 3 Bit 7 6 5 4 3 2 1 0 Byte 4 Bit 7 6 5 4 3 2 1 0 Byte 5 Bit 7 6 5 4 3 2 1 0 Byte 6 Bit 7 6 5 4 3 2 1 0 byte 20 byte 19 byte 18 byte 17 byte 16 PDC 8/30 mode Format 1 byte 15 bit 0 1 2 3 4 5 6 7 bit 0 1 2 3 4 5 6 7 bit 0 1 2 3 4 5 6 7 bit 0 1 2 3 4 5 6 7 bit 0 1 2 3 4 5 6 7 bit 0 1 2 3 4 5 6 7 byte 25 byte 24 byte 15 byte 14 byte 23 byte 22 byte 21 byte 20 byte 19 byte 18 byte 17 Format 2 byte 16 bit 0 1 2 3 bit 0 1 2 3 bit 0 1 2 3 bit 0 1 2 3 bit 0 1 2 3 bit 0 1 2 3 bit 0 1 2 3 bit 0 1 2 3 bit 0 1 2 3 bit 0 1 2 3 bit 0 1 2 3 bit 0 1 2 3 byte 15 byte 5 byte 14 byte 13 byte 12 VPS mode byte 11 bit 0 1 2 3 4 5 6 7 bit 0 1 2 3 4 5 6 7 bit 0 1 2 3 4 5 6 7 bit 0 1 2 3 4 5 6 7 bit 0 1 2 3 4 5 6 7 bit 0 1 2 3 4 5 6 7 byte 43 (35) byte 42 (34) byte 41 (33) byte 40 (32) byte 39 (31) Header time mode 1 (3) byte 38 (30) bit 0 1 2 3 4 5 6 7 bit 0 1 2 3 4 5 6 7 bit 0 1 2 3 4 5 6 7 bit 0 1 2 3 4 5 6 7 bit 0 1 2 3 4 5 6 7 bit 0 1 2 3 4 5 6 7 byte 27 (19) byte 26 (18) byte 25 (17) byte 24 (16) byte 23 (15) Header time mode 2 (4) byte 22 (14) bit 0 1 2 3 4 5 6 7 bit 0 1 2 3 4 5 6 7 bit 0 1 2 3 4 5 6 7 bit 0 1 2 3 4 5 6 7 bit 0 1 2 3 4 5 6 7 bit 0 1 2 3 4 5 6 7
Continued on next page.
No. 5834-26/32
LC74799, 74799M
Continued from preceding page.
Output data Byte 7 Bit 7 6 5 4 3 2 1 0 Byte 8 Bit 7 6 5 4 3 2 1 0 Byte 9 Bit 7 6 5 4 3 2 1 0 Byte 10 Bit 7 6 5 4 3 2 1 0 Byte 11 Bit 7 6 5 4 3 2 1 0 Byte 12 Bit 7 6 5 4 3 2 1 0 Byte 13 Bit 7 6 5 4 3 2 1 0 Bits for which data is not set are set to 1. byte 25 byte 24 byte 23 byte 22 byte 14 byte 13 PDC 8/30 mode Format 1 byte 21 bit 0 1 2 3 4 5 6 7 bit 0 1 2 3 4 5 6 7 bit 0 1 2 3 4 5 6 7 bit 0 1 2 3 4 5 6 7 bit 0 1 2 3 4 5 6 7 bit 0 1 2 3 4 5 6 7 bit 0 1 2 3 4 5 6 7 0 0 0 Error information 2 1 1 1 1 Error byte 16 17 18 19 20 21 22 23 14 15 24 25 13 0 0 Error information 2 information 1 Format 2 byte 13 bit 0 1 2 3 1 1 1 1 1 1 1 1 Error byte 11 12 13 14 5 15 byte 45 (37) information 1 VPS mode Header time mode 1 (3) byte 44 (36) bit 0 1 2 3 4 5 6 7 bit 0 1 2 3 4 5 6 7 byte 38 (30) Error 40 (32) 41 (33) 42 (34) 43 (35) 44 (36) 45 (37) 39 (31) information 2 byte 29 (21) Header time mode 2 (4) byte 28 (20) bit 0 1 2 3 4 5 6 7 bit 0 1 2 3 4 5 6 7 byte 22 (14) 23 (15) 24 (16) 25 (17) 26 (18) 27 (19) 28 (20) 29 (21)
No. 5834-27/32
LC74799, 74799M Data is output in order starting with bit 7 of byte 1. 1, 2 : 8/30/2 3, 4 : 8/30/1
Output data Byte 1 Bit 7 6 5 4 3 2 1 0 Byte 2 Bit 7 6 5 4 3 2 1 0 Byte 3 Bit 7 6 5 4 3 2 1 0 Byte 4 Bit 7 6 5 4 3 2 1 0 Byte 5 Bit 7 6 5 4 3 2 1 0 Byte 6 Bit 7 6 5 4 3 2 1 0 Byte 7 Bit 7 6 5 4 3 2 1 0 byte 32 (32) byte 31 (31) byte 30 (30) byte 29 (29) byte 28 (28) byte 27 (27) Status display mode 1 (3) byte 26 (26) bit 0 1 2 3 4 5 6 7 bit 0 1 2 3 4 5 6 7 bit 0 1 2 3 4 5 6 7 bit 0 1 2 3 4 5 6 7 bit 0 1 2 3 4 5 6 7 bit 0 1 2 3 4 5 6 7 bit 0 1 2 3 4 5 6 7 byte 42 (42) byte 41 (41) byte 40 (40) byte 39 (39) byte 38 (38) byte 37 (37) Status display mode 2 (4) byte 36 (36) bit 0 1 2 3 4 5 6 7 bit 0 1 2 3 4 5 6 7 bit 0 1 2 3 4 5 6 7 bit 0 1 2 3 4 5 6 7 bit 0 1 2 3 4 5 6 7 bit 0 1 2 3 4 5 6 7 bit 0 1 2 3 4 5 6 7 PAL Puls bit 0 1 2 3 4 5 6 7 bit 8 9 10 11 12 13 0 0
Continued on next page.
No. 5834-28/32
LC74799, 74799M
Continued from preceding page.
Output data Byte 8 Bit 7 6 5 4 3 2 1 0 Byte 9 Bit 7 6 5 4 3 2 1 0 Byte 10 Bit 7 6 5 4 3 2 1 0 Byte 11 Bit 7 6 5 4 3 2 1 0 Byte 12 Bit 7 6 5 4 3 2 1 0 Byte 13 Bit 7 6 5 4 3 2 1 0 Bits for which data is not set are set to 1. Error information 2 Error information 1 byte 35 (35) byte 34 (34) Status display mode 1 (3) byte 33 (33) bit 0 1 2 3 4 5 6 7 bit 0 1 2 3 4 5 6 7 bit 0 1 2 3 4 5 6 7 byte 26 (26) 27 (27) 28 (28) 29 (29) 30 (30) 31 (31) 32 (32) 33 (33) byte 34 (34) 35 (35) 0 0 0 0 0 0 Error information 2 Error information 1 byte 45 (45) byte 44 (44) Status display mode 2 (4) byte 43 (43) bit 0 1 2 3 4 5 6 7 bit 0 1 2 3 4 5 6 7 bit 0 1 2 3 4 5 6 7 byte 36 (36) 37 (37) 38 (38) 39 (39) 40 (40) 41 (41) 42 (42) 43 (43) byte 44 (44) 45 (45) 0 0 0 0 0 0 PAL Puls
No. 5834-29/32
LC74799, 74799M Display Screen Structure The display consists of 12 lines of 24 characters. Up to 288 characters can be displayed. The number of characters that can be displayed is reduced from the 288 maximum when enlarged characters are displayed. Display memory addresses are specified as row (0 to B hexadecimal) and column (0 to 17 hexadecimal) addresses. Display Screen Structure (display memory addresses)
24 Characters
12 Rows
No. 5834-30/32
LC74799, 74799M Composite Video Signal Output Levels (internally generated levels) CVOUT output level waveform (VDD2 = 5.00 V)
Output level VCHA VRSH VCBH VRSL VBK1 VBK0 VPD VCBL VSN : Character : Background color high : Color burst high : Background color low : Frame : Frame : Pedestal : Color burst low : Sync
Output voltage (1) [V] 2.65 2.37 (2.01) 1.67 1.23 (1.16) 2.08 1.50 1.37 1.07 0.80
Output voltage (2) [V] 2.85 2.57 (2.21) 1.87 1.43 (1.36) 2.28 1.70 1.57 1.27 1.00
Output voltage (3) [V] 3.25 2.97 (2.61) 2.27 1.83 (1.76) 2.68 2.10 1.97 1.67 1.40
Note: VDD2 = 5.00V. The values in parentheses for VRSH and VRSL are the values for a blue background.
No. 5834-31/32
LC74799, 74799M
s No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of which may directly or indirectly cause injury, death or property loss. s Anyone purchasing any products described or contained herein for an above-mentioned use shall: Accept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all damages, cost and expenses associated with such use: Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors or any of their officers and employees jointly or severally. s Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of May, 1998. Specifications and information herein are subject to change without notice. PS No. 5834-32/32

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